LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--Testador Completo

ENTITY filter IS

    PORT(test_state: IN STD_LOGIC_VECTOR(4 DOWNTO 0) := "00000";
	     filter_enable: IN STD_LOGIC := '0';
        l_in: INOUT STD_LOGIC_VECTOR(7 DOWNTO 1);
        r_in: INOUT STD_LOGIC_VECTOR(7 DOWNTO 1);
	     l_out: INOUT STD_LOGIC_VECTOR(7 DOWNTO 1);
        r_out: INOUT STD_LOGIC_VECTOR(7 DOWNTO 1));

END filter;

ARCHITECTURE logic OF filter IS 

SIGNAL l_pin_enable: STD_LOGIC_VECTOR(7 DOWNTO 1) :=  "1111111";
SIGNAL r_pin_enable: STD_LOGIC_VECTOR(7 DOWNTO 1) :=  "1111111";

BEGIN

    l_in(1) <= l_out(1) WHEN l_pin_enable(1) = '1' ELSE 'Z';
    l_out(1) <= l_in(1) WHEN l_pin_enable(1) = '0' ELSE 'Z';
    l_in(2) <= l_out(2) WHEN l_pin_enable(2) = '1' ELSE 'Z';
    l_out(2) <= l_in(2) WHEN l_pin_enable(2) = '0' ELSE 'Z';
    l_in(3) <= l_out(3) WHEN l_pin_enable(3) = '1' ELSE 'Z';
    l_out(3) <= l_in(3) WHEN l_pin_enable(3) = '0' ELSE 'Z';
	 l_in(4) <= l_out(4) WHEN l_pin_enable(4) = '1' ELSE 'Z';
    l_out(4) <= l_in(4) WHEN l_pin_enable(4) = '0' ELSE 'Z';
    l_in(5) <= l_out(5) WHEN l_pin_enable(5) = '1' ELSE 'Z';
    l_out(5) <= l_in(5) WHEN l_pin_enable(5) = '0' ELSE 'Z';
    l_in(6) <= l_out(6) WHEN l_pin_enable(6) = '1' ELSE 'Z';
    l_out(6) <= l_in(6) WHEN l_pin_enable(6) = '0' ELSE 'Z';
    l_in(7) <= l_out(7) WHEN l_pin_enable(7) = '1' ELSE 'Z';
    l_out(7) <= l_in(7) WHEN l_pin_enable(7) = '0' ELSE 'Z';
	 r_in(7) <= r_out(7) WHEN r_pin_enable(7) = '1' ELSE 'Z';
    r_out(7) <= r_in(7) WHEN r_pin_enable(7) = '0' ELSE 'Z';
	 r_in(6) <= r_out(6) WHEN r_pin_enable(6) = '1' ELSE 'Z';
    r_out(6) <= r_in(6) WHEN r_pin_enable(6) = '0' ELSE 'Z';
    r_in(5) <= r_out(5) WHEN r_pin_enable(5) = '1' ELSE 'Z';
    r_out(5) <= r_in(5) WHEN r_pin_enable(5) = '0' ELSE 'Z';
    r_in(4) <= r_out(4) WHEN r_pin_enable(4) = '1' ELSE 'Z';
    r_out(4) <= r_in(4) WHEN r_pin_enable(4) = '0' ELSE 'Z';
    r_in(3) <= r_out(3) WHEN r_pin_enable(3) = '1' ELSE 'Z';
    r_out(3) <= r_in(3) WHEN r_pin_enable(3) = '0' ELSE 'Z';
    r_in(2) <= r_out(2) WHEN r_pin_enable(2) = '1' ELSE 'Z';
    r_out(2) <= r_in(2) WHEN r_pin_enable(2) = '0' ELSE 'Z';
    r_in(1) <= r_out(1) WHEN r_pin_enable(1) = '1' ELSE 'Z';
    r_out(1) <= r_in(1) WHEN r_pin_enable(1) = '0' ELSE 'Z';
	 
	 PROCESS(filter_enable, test_state)
	 BEGIN
	 IF(filter_enable = '1') THEN
	     CASE test_state IS
            WHEN "00001" =>
                l_pin_enable <= "1111100";
                r_pin_enable <= "1111111";
            WHEN "00010" =>
                l_pin_enable <= "1110101";
                r_pin_enable <= "1111111";
            WHEN "00011" =>
                l_pin_enable <= "1110100";
                r_pin_enable <= "1111111";
			   WHEN "10001" =>
                l_pin_enable <= "1100100";
                r_pin_enable <= "1100100";
			   WHEN "10010" =>
                l_pin_enable <= "1101010";
                r_pin_enable <= "1101010";
			   WHEN "10011" =>
                l_pin_enable <= "1100000";
                r_pin_enable <= "1100010"; 
			   WHEN "10100" =>
                l_pin_enable <= "1100100";
                r_pin_enable <= "1100100";
			   WHEN "10101" =>
                l_pin_enable <= "1110110";
                r_pin_enable <= "1000000";
			   WHEN "10110" =>
                l_pin_enable <= "0000000";
                r_pin_enable <= "1111111";
			   WHEN "10111" =>
                l_pin_enable <= "1000000";
                r_pin_enable <= "1000000";
			   WHEN "11000" =>
                l_pin_enable <= "0000000";
                r_pin_enable <= "0011111";
			   WHEN "11001" =>
                l_pin_enable <= "0111100";
                r_pin_enable <= "0000000";	 
            WHEN "11111" =>
                l_pin_enable <= "0000000";
                r_pin_enable <= "0000000";
            WHEN OTHERS =>
                l_pin_enable <= "1111111";
                r_pin_enable <= "1111111";
        END CASE;
    ELSE
        l_pin_enable <= "1111111";
        r_pin_enable <= "1111111";
    END IF;
	 
	 END PROCESS;

END logic;